Referring to FIG. 1, a conventional IGBT comprises a p.sup.++ -type emitter layer 1, an n.sup.+ -type buffer layer 2, an n.sup.- -type base layer 3, a p-type base region 4, an n.sup.+ -type source region 5, an insulating layer 6, a gate electrode 7, a cathode electrode 8, and an anode electrode 9. The conventional IGBT has both a hole current 10 and an electron current 11 flowing though it.
The p-type base region 4 is embedded in an upper region of the n.sup.- -type base layer 3, and the n.sup.+ -type source region 5 is further embedded in the p-type base region 4. The gate electrode 7 is formed over the n.sup.- -type base layer 3, and is wholly enclosed by the insulating layer 6. The p-type base region 4 and the n.sup.+ -type source region 5 are electrically connected to the cathode electrode 8. The n.sup.+ -type buffer layer 2 is formed on the lower side of the n.sup.- -type base layer 3. In addition, the p.sup.++ -type emitter layer 1, electrically connected with the anode electrode 9, is formed on the lower side of the buffer layer 2. In operation, the hole current 10 flows from the anode electrode 9 to the cathode electrode 8, and the electron current 11 flows in a reverse direction.
The equivalent circuit of FIG. 1 is shown in FIG. 2. This equivalent circuit includes the gate electrode 7, the cathode electrode 8, the anode electrode 9, an NMOS transistor 12, an NPN transistor 13, a PNP transistor 14, first through third nodes 15-17, and a resistor R.sub.b.
The NMOS transistor 12 is connected in parallel with the NPN transistor 13. The NMOS transistor 12 has its current path connected between the first and second nodes 15 and 16, and its gate connected to the gate electrode 7. The NPN transistor 13 has its emitter connected to the first node 15, its collector connected to the second node 16, and its gate connected to the third node 17. The PNP transistor 14 has its collector connected to the third node, its emitter connected to the cathode electrode 8, and its base connected to the second node 16. The resistor R.sub.b is connected between the third node 17 and the cathode electrode 8. In addition, the first node 15 is connected to the cathode electrode 8.
In the conventional IGBT described above, latch-up is caused by the hole current 10 flowing in the lower part of the n.sup.+ -type source region 5 and its resistance R.sub.b. More specifically, the hole current 10 and resistance R.sub.b increase the voltage between the p/n junction on the right side of the n.sup.+ -type source region 5. Hence, a charge transfer injection occurs in the p/n junction so that the electrons flow from the n.sup.+ -type source region 5 to the n.sup.- -type base layer 3 without passing the channel below the gate electrode 7. This causes latch-up since the current is not cut off from the device even when a negative voltage is applied to the gate electrode 7.
The latch-up determines the maximum current allowable for the device, and the time that the device can endure a short circuit. The short circuit causes high voltage and high current to be applied to the device, rapidly increasing its temperature. This in turn lowers the voltage required to initiate the charge transfer injection in the p/n junction between the p-type base region 4 and the n.sup.+ -type source region 5. As a result of this, current cannot be prevented from flowing into the device if the operation of the protection circuit is delayed, and the device can be destroyed.